Where a microprocessor forms part of a system it is common practice for an external device to interrupt the microprocessor program flow, and to have the microprocessor service the interrupt. Examples of such interrupt systems are discussed in U.S. Pat. No. 4,349,873.
Typically, the microprocessor receives the interrupt signal and when the microprocessor completes the current instruction, the microprocessor jumps directly or indirectly to a routine to service the interrupt. Once the interrupt is serviced, the microprocessor may return to its earlier program thread and continues to execute that thread. Although the above described interrupt process is effective and popular, it does have several drawbacks—due to the need to complete the current instruction or software task, the time between reception of an interrupt signal and servicing the response can vary, and a significant number of machine cycles may occur before the interrupt is serviced. Interrupt response times may vary, due to factors such data cache misses or instruction cache misses caused by the main computer program. A significant number of machine cycles are usually required to perform context switching to ensure integrity of the main program.
Additionally, if a microprocessor is waiting for an external signal, for example when the microprocessor is performing a loop, it consumes power while doing so.
This idle time may be relatively long as there can be significant overhead when servicing an interrupt. This is particularly true if the microprocessor is to ensure that a temporary data storage area is provided and that data transfer is synchronised so that data is not read before being stored, or overwritten before being read.
Further, this traditional approach to handling interrupt does not work well with more modern techniques for improving microprocessor speed and efficiency. For example, Microprocessors today often have a branch prediction mechanism to minimise the overhead incurred by branches in normal program flow. External interrupts often compromise the prediction mechanism due to their highly unpredictable nature.
Accordingly, there is a need in the art for improved techniques for handling interprocessor communications.